1. Field of the Invention
The present invention relates to a logic circuit composed of insulated gate field-effect transistors (hereinbelow termed "MISFETs"). More particularly, it relates to a MISFET logic circuit having a depletion type load transistor.
2. Description of the Prior Art
As the general logic circuit employing MISFETs, the so-called EE (enhancement-enhancement) system is known in which both MISFETs for a load and for drive are of the enhancement type. As means to reduce the power consumption of the above system, there is the clock drive system in which the load transistor is driven by clock pulses.
On the other hand, with the so-called ED (enhancement-depletion) system employing a depletion type MISFET as a load transistor, it is difficult to adopt the clock drive system similar to that of the EE system. Nevertheless, excellent properties such as low power consumption, high speed and high degree of integration are available due to the possibility of a low supply voltage and the constant current characteristic of the depletion type MISFET.
FIG. 5 shows the fundamental circuit of a logic circuit according to the ED system.
To be noted in regard to the fundamental circuit in the figure is the fact that, whenever drive transistor Q.sub.d is conductive, current flows through a series circuit consisting of the drive transistor Q.sub.d and load transistor Q.sub.1.